It is very simple. For +VCC, just add a DC voltage Between the ground and the diode cathode at the output. The DC voltage has the symbol like a battery with the positive terminal to the diode and the negative terminal to ground. For -VCC, do the same, but with the inverted battery.

can you please give a clear image of how that will be added in the opamp modelling and also how it will affect if not added?
Also will be perfect if you add a schematic to show the connection

Place a diode between output and +Vcc with the anode connected to output. Also, place a diode between -Vcc and output with the anode connected to -Vcc.

Actually, many op amp datasheets have the input resistance specified. It depends on the manufacturer. Take a look at Analog Devices amplifiers. Here are some examples, ADA4896, ADA4528, ADA4891, ADA4898, ADA4051, ADA4062, ADA4075, just to mention a few. However, if the input resistance is missing, I would divide the specified maximum input common mode voltage to the bias current to get the common mode resistance, ballpark number. With that, you can estimate the differential input resistance, by dividing the common mode resistance by 10…100.

Thank you Eric for your input. That’s exactly why I wrote this series.

It wasn’t that long ago that we had to go through the whole process of building a similar model for a transformer, complete with all the parasitics, so we feel for you. In our case, though, the model was somewhat simpler (at least as was required in our application) but the datasheets even sketchier. And before we were done, we were measuring values with an LRC meter that that magnetics manufacturer was either unwilling or unable to publish.

Srihari, THD and Harmonics cannot be modeled with a behavioral method. You need to recreate the Op Amp with non-linear elements like transistors and diodes. They are the source of distortions. That is why semiconductor companies release SPICE models for their components, because the Op Amp design engineers intimately know the component schematic and the process through which the Op Amp is grown on the silicon wafer. With a macro model as described in this article one can do as much, to accurately test a DC schematic and some AC behavior. Each model has its limitations, and that is why one has to understand the underlying physics and know how much he can trust the model.

I’m glad you find this article useful. Thank you for visiting.

As per the understanding
90db = 31623 gain
BW = GBP/open loop gain = 200Mhz/31623 = 6.324kHz cutoff freq
Therefore with gm=1Mho R=31.623k C=1/2piRC = 0.8nF
First order model is developed, but to get small signal bw of 118MHz i scalled C to 1.342nF because 200M/118M = 1.69 so 1.69*0.8nF = 1.342nF
Now a VCVS at the output with Gain of 1 will give the desired result for dominant pole, bw etc. If we are to introduce THD, HD2, HD3 we need to introduce noise at VCVS with some coefficient.
Can you please help me how to model this THD, HD2, HD3 in spice.
Thanks
Srihari