An ADC and DAC Differential Non-Linearity (DNL)

As in the case of INL, DNL is an important parameter of an ADC or DAC because it is a measure of their non-linearity.  DNL stands for Differential Non-Linearity and quantifies the ADC or DAC precision.

The term differential refers to the values an ADC takes between two consecutive levels.  When the input signal swings in any direction, the ADC samples the signal and its output is a stream of binary numbers.  An ideal ADC will step up or down one Least Significant Bit (LSB), without skipping any level and without holding the same decimal number past two or three LSBs. However, due to technological limitations, ADCs and even DACs are not ideal.  When that happens, the ADC’s linearity is severely impacted.  Therefore, DNL is defined as the maximum deviation from one LSB between two consecutive levels, over the entire transfer function.

In an electronic system, linearity is important.  When an ADC is non-linear, it brings imprecision in measurements.  If a DAC is non-linear, it restores a dynamic signal with high distortions.  Moreover, an accumulation of skipped levels, or high DNL, can increase the INL as well.

Figuring out the DNL value is quite simple. One has to measure the ADC response to a voltage value that would correspond to one LSB. For example, if we have a 12-bit ADC and the voltage reference is 2.5V, one LSB is given by the following equation.


So, for each 0.6103 mV increase in the ADC input, the output hexadecimal value will increase with one.


Figure 1

An ideal ADC transfer function is shown in Figure 1.  This is a 12-bit ADC, but the steps are exaggerated for better viewing.  There is no deviation from 1 LSB step, so the DNL is zero.


Figure 2

In Figure 2, the ADC holds the 0x800 hex output for two full steps. Since the deviation is towards the positive values on the X scale, and the ADC output holds the same value for an extra LSB, the Differential Non-Linearity is +1 LSB.


Figure 3

Figure 3 shows that the DNL migrated towards negative values for one LSB. Therefore, DNL in Figure 3 is -1 LSB. Since 0x800 is missing, there the ADC is categorized with missing codes.  Such an ADC cannot be used for high precision applications.

The DNL in Figure 4 is -0.75, because the 0x800 is still there, but for a shorter voltage range than one LSB.  The code is still there, so the ADC can be used in precision applications.


Figure 4

In Figure 5, the 0x800 step appears at lower voltage inputs than one LSB.  The DNL is -1.25 LSB. It is clear that the ADC is highly non-linear.  Moreover, it is categorized non-monotonic.  High DNL values, positive or negative can increase the INL as well.


Figure 5

A non-monotonic DAC is highly undesirable, especially if the DAC is used in a closed loop application like servo or process controls.  With a non-monotonic DAC the system may become unstable, or the control may suffer from jumpiness, jitteriness and overall difficult control handling.

The main rule for precision applications is to choose a component with a DNL less than one LSB. In this case, the ADC or DAC is assured monotonicity, no missing codes and a good linearity.

An ADC and DAC Integral Non-Linearity (INL)

What is INL?  This term describes the non-linearity of Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC).  INL stands for Integral Non-Linearity.  Is this term important? Should we be concerned about this specification?  The answer is yes.

INL is considered an important parameter because it is a measure of an ADC or DAC non-linearity error.  However, as in any Analog or Mixed-Signal Design project, some specifications are important, some are not.  It all depends on the project requirements regarding accuracy and precision.  Understanding INL enables the circuit designer to avoid surprises in his or her project.

The Integral Non-Linearity is defined as the maximum deviation of the ADC transfer function from the best-fit line.  An ADC function is to digitize a signal into a stream of digital words called samples.  The ADC output is discrete as opposed to the input, which is continuous.  It is used at the boundary between the analog and digital realms.

The ADC input is usually connected to an operational amplifier, maybe a summing or a differential amplifier which are linear circuits and process an analog signal.  As the ADC is included in the signal chain, we would like the same linearity to be maintained at the ADC level as well.  However, inherent technological limitations make the ADC non-linear to some extent and this is where the INL comes into play.


Figure 1

Figure 1 shows the ADC transfer function.  For each voltage in the ADC input there is a corresponding word at the ADC output.  The figure shows a 12-bit ADC where the steps were exaggerated for better viewing.  The y axis, the output, is digital, so that the values are represented in hexadecimal format.  If the ADC is ideal, the steps shown are perfectly superimposed on a line.


Figure 2

Figure 2 shows an ADC with a slight non-linearity.  To express the non-linearity in a standard way, manufacturers draw a line through the ADC transfer function, called the best fit line.  The maximum deviation from this line is called INL, which can be expressed in percentage of the full scale or in LSBs (List Significant Bit). INL is measured from the center of each step to that point on the line, where the center of the step would be if the ADC was ideal.

This parameter is important because it cannot be calibrated out.  The ADC non-linearity is unpredictable.  We don’t know where on the ADC scale the maximum deviation from the ideal line is.  Therefore, if one of the design requirements is good accuracy, we need to choose an ADC with the INL within the accuracy specifications, or a lot less than the specified error.

For example, let’s say the electronic device we design has an ADC that needs to measure the input signal with a precision of 0.5% of full-scale.  Due to the ADC quantization, if we choose a 12-bit ADC, the initial measurement error is +/- 1/2 LSB which is called the quantization error.


With the ADC quantization error almost 40 times lower than the design requirements, a 12-bit ADC can do a good job for us.  However, if the INL is large, the actual ADC error may come close to the design requirements of 0.5%.  We would like to keep each component error in the circuit as low as possible, so that the total combined error of the electronic device we design is less than 0.5%.  Gain or offset errors in an ADC can be calibrated out, but INL cannot.  If we need to live with an evil, at least we need to choose an ADC with a small INL.  This may increase the cost we allocate for the ADC in the system, but it is worthwhile if we are to keep our promises and design a device within specifications.

The DAC Integral Non-Linearity can be viewed the same as for an ADC.  The only difference is that, with a DAC, the INL may not be as important.  If the DAC is used to set a few voltage levels in a system, those values may be easily calibrated, so we can choose a low cost DAC.  However, if the DAC is used to accurately restore a dynamic signal, the INL cannot be easily calibrated.  In that case, we need to choose a high precision DAC, with a good INL.

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